The present invention relates generally to integrated circuits and in particular the present invention relates to the self-alignment of separated regions in a lateral MOSFET structure of an integrated circuit.
Integrated circuits incorporating high voltage lateral elements include both metal-oxide-semiconductor field-effect transistors (MOSFETs) devices and bipolar junction transistors. A common use of a power MOSFET in an integrated circuit is as an electronic switch. One known high-voltage MOSFET structure for an integrated circuit includes a drain contact connected to the drain end of a channel by a lateral drain extension, which has the same conductively type as the drain contact. High voltage breakdown is achieved by designing the drain extension with an integrated doping (dopant ions per cm2) such that the drain extension totally depletes at high drain voltages, before the point where avalanche breakdown occurs at a pn junction between the drain extension and the MOSFET body.
Along with size of the structure, there are two other key characteristics of a MOSFET when used in an integrated circuit as an electronic switch. The first is its breakdown voltage and the second is its ON resistance. The breakdown voltage is a measure of the MOSFET""s ability to withstand a reversed bias voltage when it is in an OFF or open condition. The ON resistance is a measure of the resistance when the MOSFET is in an ON or closed condition. Improving the operation of the MOSFET switch in an integrated circuit suggests a breakdown voltage as high as possible and an ON resistance as low as possible. A perfect switching device has an infinite breakdown voltage and zero ON resistance. Accordingly, it is desired in the art to reduced the ON resistance. One way of reducing the ON resistance of a lateral MOSFET device is to accurately align various regions of the MOSFET to achieve predefined space between the regions. Unfortunately this is difficult to do with existing techniques because mask edges used to form the various regions introduce an uncertainty factor called an alignment tolerance that contributes to the space between the regions.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art there is a need for a method of accurately controlling the distance between various regions in integrated circuits.
The above mentioned problems with integrated circuits with high voltage MOSFETs and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of forming a MOSFET device in an integrated circuit is disclosed. The method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants of the first conductivity type in the substrate to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants of a second conductivity type with high dopant density to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.
In another embodiment, a method of forming a lateral MOSFET device in an integrated circuit. The method comprising, forming a dielectric layer on a surface of a substrate, wherein the dielectric layer has a relatively thick dielectric region and a relatively thin dielectric region. Forming a gate electrode overlaying a portion of the relatively thin dielectric region. Introducing a first conductivity type dopant to form a top gate region along the surface of the substrate, wherein a first edge of the top gate region is defined by a second edge of the gate electrode and a second edge of the top gate region is defined by a first edge of the relatively thick dielectric region. Introducing a second conductivity type dopant with a high dopant density to form a first region of the second conductivity type along the surface of the substrate, wherein a first edge of the first region is defined by a second edge of the relatively thick dielectric region. Moreover, the first edge of the first region is separated from the second edge of the top gate region by a lateral length of the relatively thick dielectric region.
In another embodiment, a method of forming a lateral MOSFET device in an integrated circuit. The method comprising, forming a dielectric layer on a surface of a substrate. The dielectric layer has a relatively thick dielectric region and a relatively thin dielectric region. Forming a gate electrode overlaying a portion of the relatively thin dielectric region. Introducing a first conductivity type dopant to form a top gate region along the surface of the substrate, wherein a first edge of the top gate region is defined by a second edge of the gate electrode and a second edge of the top gate region is defined by a first edge of the relatively thick dielectric region. Introducing a second conductivity type dopant with a high dopant density to form a first region of the second conductivity type along the surface of the substrate, wherein a first edge of the first region is defined by a second edge of the relatively thick dielectric region. Moreover, the first edge of the first region is separated from the second edge of the top gate region by a lateral length of the relatively thick dielectric region.
In another embodiment, a method of forming a high voltage MOSFET for an integrated circuit. The method comprising, forming a relatively thin layer of dielectric on a surface of a substrate. Depositing a gate material layer on the relatively thin layer of dielectric, removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, wherein the top gate is formed adjacent the surface of the substrate and laterally between the first and second gate material regions. Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein the second gate material region is positioned laterally between the drain region and the top gate. In addition, the spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.
In another embodiment, a method of forming a lateral MOSFET in an integrated circuit. The method comprising, forming a drain contact of a second conductivity type with a high density dopant in a substrate adjacent a surface of the substrate. Forming a top gate of the first conductivity type in the substrate adjacent the surface of the substrate and a predetermined distance from the drain contact after the drain contact is formed. In addition, the drain contact is formed to extend deeper from the surface of the substrate than the top gate and is formed to have a higher dopant density at every depth than the top gate so a mask is not needed to shield the drain contact from the first conductivity dopants during formation of the top gate.
In another embodiment, a method of forming a pn junction diode in an integrated circuit is disclosed. The method comprising, forming a first region of relatively thick material on the surface of a substrate. Forming a second region of relatively thick material on the surface of a substrate a predetermined distance from the first region. Implanting high density of dopants of the second conductivity type in the substrate to form a cathode contact using first edges of the first and second regions as masks to define edges of the cathode contact, wherein the cathode contact is positioned between the first and second regions. Implanting dopants of the first conductivity type in the substrate to form first and second top gate regions using second edges of the first and second regions as masks to define first edges of the first and second top gate regions, wherein the distance between the cathode contact and the first top gate region is defined by the lateral length of the first region and the distance between the cathode contact and the second top gate region is defined by the lateral length of the second region. Implanting high density dopants of the first conductivity type in the substrate to form first and second anode contact regions.
In another embodiment, a method of forming a high voltage bipolar transistor in an integrated circuit is disclosed. The method comprising, forming a first region of relatively thick material on a surface of a substrate. Forming a second region of relatively thick material on the surface of the substrate a predefined distance from the first region. Introducing dopant of a second conductivity type to form a base region in the substrate using first edges of the first and second regions to form edges of the base region, wherein the base region is positioned between the first and second regions. Introducing dopants of the first conductivity type to form a first top gate using a second edge of the first region as a mask to form an edge of the first top gate, wherein the distance between the first top gate and the base region is defined by the lateral length of the first region. Introducing dopants of the first conductivity type to form a second top gate using a second edge of the second region as a mask to form an edge of the first top gate, wherein the distance between the second top gate and the base region is defined by the lateral length of the second region.
In another embodiment, a lateral MOSFET for an integrated circuit is disclosed. The lateral MOSFET comprising a substrate, a relatively thin layer of dielectric, a first region of relatively thick material, a drain contact and a first top gate. The relatively thin layer of dielectric is formed on a surface of the substrate. The first region of relatively thick material is formed on the surface of the substrate adjacent the relatively thin dielectric material. The first region has a predefined lateral length. Moreover, the first region can mask dopants from penetrating the surface of the substrate. The drain contact region is of a second conductivity type with high dopant density. It is formed in the substrate adjacent the surface of the substrate. The first region is used as a mask to form a first edge of the drain contact. The first top gate is of the first conductivity typed and is formed in the substrate adjacent the surface of the substrate. The first region is used as a mask to form a first edge of the first top gate. The distance between the drain contact region and the first top gate is defined by the lateral length of the first region.
In another embodiment, a lateral MOSFET for an integrated circuit is disclosed. The lateral MOSFET of this embodiment comprises a substrate, a relatively thick dielectric region, a relatively thin dielectric region, a gate electrode, a first top gate region, a drain region and a source. The relatively thick dielectric region is formed on a surface of the substrate. The relatively thick dielectric region has a predetermined lateral length. The relatively thin dielectric region is formed on the surface of the substrate. The gate electrode is deposited on the relatively thin dielectric region. The first top gate region of the first conductivity type is formed in the substrate adjacent the surface of the substrate and between the gate electrode and the relatively thick dielectric region. The drain region of a second conductivity type has a high donor density formed in the substrate adjacent the surface of the substrate and adjacent the relatively thick dielectric region. The relatively thick dielectric region is used as a mask to define a lateral distance between the first top gate region and the drain region. The source region of the second conductivity type having a high donor density formed in the substrate adjacent the surface of the substrate. The gate electrode is laterally positioned between the source region and the first top gate.
In another embodiment, a solid state relay integrated circuit is disclosed. The solid state relay comprises a photo diode stack, a first high voltage MOSFET and a second high voltage MOSFET. The photo diode stack is used to drive a voltage and has a first output and a second output. The first high voltage MOSFET has a gate, source and drain. The gate of the first high voltage MOSFET is coupled to the first output of the photo diode stack. The source of the first high voltage MOSFET is coupled to the second output. The second high voltage MOSFET has a gate, source and drain. The gate of the second high voltage MOSFET is coupled to the first output of the photo diode stack. The source of the second high voltage MOSFET is coupled to the second output of the photo diode stack. The first and second high voltage MOSFETs each comprise a substrate, a relatively thin layer of dielectric, a first region of relatively thick material, a drain contact region and a top gate. The relatively thin layer of dielectric is formed on a surface of the substrate. The first region of relatively thick material is formed on the surface of the substrate adjacent the relatively thin dielectric material and has a predefined lateral length. The first region can mask dopants from penetrating the surface of the substrate. The drain contact region is of a second conductivity type with high dopant density and is formed in the substrate adjacent the surface of the substrate. The first region is used as a mask to form a first edge of the drain contact. The first top gate of the first conductivity typed is formed in the substrate adjacent the surface of the substrate. The first region is used as a mask to form a first edge of the first top gate. Moreover, the distance between the drain contact region and the first top gate is defined by the lateral length of the first region.
In another embodiment, a pn junction for an integrated circuit is disclosed. The pn junction for an integrated circuit comprises a substrate, a first and second region of relatively thick material, a cathode contact, a first and second top gate and a first and second anode contact. The first region of relatively thick material is formed on a surface of the substrate. The second region of relatively thick material is formed on the surface of the substrate a predetermined lateral distance from the first region. The cathode contact is of a second conductivity type with high dopant density and is formed in the substrate adjacent the surface of the substrate. The cathode contact is positioned between the first and second regions, wherein first edges of the first and second regions are used as a mask to define the edges of the cathode contacts. The first top gate of the first conductivity type formed in the substrate adjacent the surface of the substrate. A first edge first top gate is positioned adjacent a second edge of the first region. Moreover, the second edge of the first region is used as a mask to form the first edge of the first top gate. The lateral length of the first region defines the lateral distance between the first top gate and the cathode contact. The second top gate of the first conductivity type is formed in the substrate adjacent the surface of the substrate. A first edge of the second top gate is positioned adjacent a second edge of the second region. Moreover, the second edge of the second region is used as a mask to form the first edge of the second top gate. The lateral length of the second region defines the lateral distance between the second top gate and the cathode contact. The first anode contact is of the first conductivity type with high dopant density and is formed in the substrate adjacent the surface of the substrate and a predetermined distance from the first top gate. The second anode contact is of the first conductivity type with high dopant density and is formed in the substrate adjacent the surface of the substrate and a predetermined distance from the second top gate.
In another embodiment, a high voltage bipolar transistor for an integrated circuit is disclosed. The high voltage bipolar transistor for an integrated circuit comprises a substrate, a first and second region of relatively thick material, a base region and a first and second top gate. The first region is of a relatively thick material formed on a surface of a substrate. The second region also of a relatively thick material formed on the surface of the substrate a predefined distance from the first region. The base region is of a second conductivity type formed in the substrate using first edges of the first and second regions to form edges of the base region. The base region is positioned between the first and second regions. The first top gate of the first conductivity type is formed in the substrate using a second edge of the first region as a mask to form an edge of the first top gate. The distance between the first top gate and the base region is defined by the lateral length of the first region. The second top gate of the first conductivity type is formed in the substrate using a second edge of the second region as a mask to form an edge of the first top gate. The distance between the second top gate and the base region is defined by the lateral length of the second region.